Five Year Gap: The Costly Reality of Bypassing EUV in China

Chinese semiconductor manufacturers have developed methods to produce advanced silicon without using the extreme ultraviolet lithography machines currently restricted from the region. By relying on older deep ultraviolet equipment and employing multiple exposure techniques, firms like SMIC have created processors that approach the capabilities of leading Western standards. However, industry experts indicate that this workaround comes with substantial financial and technical penalties, including higher defect rates and longer production cycles.

The primary obstacle to China's chip advancement has been its lack of access to ASML's EUV tools. These machines use 13.5 nanometer wavelength light to etch the finest features on modern processors. Because ASML is the sole provider of this technology, analysts estimate a performance gap of five years or more between Chinese and Western manufacturing capabilities. Despite this barrier, domestic producers have demonstrated significant progress in recent years.

Evidence of this progress includes a 2023 teardown of the Huawei Mate 60 Pro, which revealed that the Kirin 9000S processor was fabricated by SMIC using a second-generation 7 nanometer class process without EUV. More recent analysis suggests the Kirin 9030 utilizes a DUV based process that approaches the density of 5 nanometer manufacturing, though it still lags behind the top-tier processes from TSMC and Samsung. This advancement is achieved through multiple patterning, where complex designs are broken into simpler patterns and built up in sequential steps.

Chris Mack, co-founder and CTO of Fractilia, notes that the focus on producing chips without EUV often overlooks the associated trade-offs. Industry standards suggest that three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, when a design requires four masks, EUV becomes the more economical choice. Furthermore, each additional exposure increases the risk of alignment errors and process variation, which can lead to larger chip sizes and fewer usable dies per wafer.

The economic impact is evident in the memory sector. Morgan Stanley reported in June that Chinese DRAM maker CXMT produces approximately one-third as many bits per wafer as its Western competitors. The bank described lithography access as a hard ceiling for Chinese memory development. While Mack notes that node labels like 5 nanometer have limited meaning in isolation, he emphasizes that SMIC's N+3 process remains significantly less scaled than established 5 nanometer processes from major rivals.

Despite these challenges, DUV technology still has potential. Micron successfully developed its 1-alpha DRAM without EUV, and Morgan Stanley believes CXMT can achieve similar results for its HBM3e plans. Douglas Fuller of Copenhagen Business School expects advanced packaging to allow DUV to remain viable for the latest DRAM generations by the end of the decade. Mack adds that China could make further strides if it fully leverages the 193 immersion ecosystem, although he notes memory production is generally easier than logic chips.

Chinese firms can continue to push DUV limits by accepting larger dies or lower yields, or by expanding capacity. Morgan Stanley projects CXMT will increase its global DRAM bit supply share from 14% in 2026 to 16% in 2028. The bank also anticipates China's AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, even as gaps persist in EUV, HBM, and advanced software.